Technical Report Number
Multiple processor interconnection networks can be characterized as having N' inputs and N' outputs, each B' bits wide. Construction of large networks requires partitioning of the N'*N'*B' network into a collection of N*N switch modules of data size B (B
Franklin, Mark A. and Wann, Donald F., "PIN Limitations and VLSI Interconnection Networks" Report Number: WUCS-81-02 (1981). All Computer Science and Engineering Research.
Permanent URL: http://dx.doi.org/10.7936/K79885BC