Document Type

Technical Report

Publication Date

1981-04-01

Filename

WUCS-81-02.pdf

DOI:

10.7936/K79885BC

Technical Report Number

WUCS-81-02

Abstract

Multiple processor interconnection networks can be characterized as having N^1 inputs and N^1 outputs, each B^1 bits wide. Construction of large networks requires partitioning of the N^1*N*1*B^1 network into a collection of N*N switch modules of data size B (B

Comments

Permanent URL: http://dx.doi.org/10.7936/K79885BC

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