Technical Report Number
Multiple processor interconnection networks can be characterized as having N^1 inputs and N^1 outputs, each B^1 bits wide. Construction of large networks requires partitioning of the N^1*N*1*B^1 network into a collection of N*N switch modules of data size B (B
Franklin, Mark A. and Wann, Donald F., "PIN Limitations and VLSI Interconnection Networks" Report Number: WUCS-81-02 (1981). All Computer Science and Engineering Research.