Title

PIN Limitations and VLSI Interconnection Networks

Authors

Mark A. Franklin, Washington University in St. LouisFollow
Donald F. Wann, Washington University in St. Louis

Document Type

Technical Report

Publication Date

1981-04-01

Filename

WUCS-81-02.pdf

DOI:

10.7936/K79885BC

Technical Report Number

WUCS-81-02

Abstract

Multiple processor interconnection networks can be characterized as having N' inputs and N' outputs, each B' bits wide. Construction of large networks requires partitioning of the N'*N'*B' network into a collection of N*N switch modules of data size B (B

Comments

Permanent URL: http://dx.doi.org/10.7936/K79885BC

Recommended Citation

Franklin, Mark A. and Wann, Donald F., "PIN Limitations and VLSI Interconnection Networks" Report Number: WUCS-81-02 (1981). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/884