Document Type

Technical Report

Publication Date

1981-04-01

Filename

WUCS-81-01.pdf

Technical Report Number

WUCS-81-01

Abstract

Interest in tightly coupled multiprocessor computer systems has grown as the possibilities for high performance with such systems have been recognized. Central to their design is the structure of the network over which the processors communicate. Unless properly designed, such networks can be both a cost and performance bottleneck. This paper focuses on the design of VLSI communications networks, this is, on communications network which can be placed on a single VLSI chip. Traditional SSI-based boost and complexity measures for such networks have principally involved switch aggregate counts. In a VLSI domain, however, more appropriate measures involve chip area, and space-time product. The effects of network topology and VLSI layout on these measures are reviewed with regard to two network types. Another important question related to the VLSI communication network problem related to the chip pin constraints. This problem is discussed and some effects and options presented by bit slice network designs are described.

Comments

Permanent URL: http://dx.doi.org/10.7936/K72V2DF1

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