Date of Award
Summer 9-7-2023
Degree Name
Doctor of Philosophy (PhD)
Degree Type
Dissertation
Abstract
The sea of hardware features is vast. Hardware features range from things as simple and small as a bypass line in the datapath of a processor to as large and complicated as a cache or accelerator. Qualitatively, hardware designers choose what functionality the design will have through the instruction set architecture (ISA). Will the processor support floating-point instructions? Will the processor's applications require SIMD or cryptography instructions? These considerations lie on a spectrum from limited or specialized ISAs to full featured general processing ISAs. This spectrum intersects with the quantitative spectrum of the microarchitecture. A processor must reach the die area, electrical power, and performance targets in its design. Generally, this ranges from small, low powered, and slow processors to large, power hungry, and fast processors. Should the processor have 4 or 8 cores? How deep should the datapath be? How many levels of cache should the processor contain? To build a hardware characterization, designers carefully select different features to satisfy functional requirements while attempting to satisfy space, power, and performance constraints along the way. We envision a hardware characterization that can evolve both qualitatively and quantitatively. In a feature-oriented characterization of an ISA, say RISC-V, hardware designers could easily swap their features for others. This could open up a marketplace of hardware features where designers could test and create features collaboratively. With a common ISA and feature-oriented characterization, researchers could better understand the nature of hardware components by reducing the variability between different hardware implementations. Instead of starting from scratch, the characterizations could build upon already established features. In this dissertation we work towards this goal of feature-oriented hardware characterization by exploring novel hardware characterization techniques through feature-oriented programming.
Language
English (en)
Chair
Ron Cytron