Date of Award
Spring 5-15-2023
Degree Name
Master of Science (MS)
Degree Type
Thesis
Abstract
Design automation of analog circuits has been a longstanding challenge in the integrated circuit field. Recently, multiple methods based on learning or optimization have demonstrated great promise in automating device sizing for analog circuits. However, they often ignore the strong susceptibility of analog circuits to process, voltage, and temperature (PVT) variations or suffer from low sampling efficiency to train algorithms. To address these critical limitations, this thesis proposes RoSE, the first Robust analog circuit parameter optimization framework with high Sampling Efficience by synergistically combining Bayesian Optimization (BO) and reinforcement learning (RL). Its core is to use the fast convergence of BO to find an optimized starting point for the backbone RL agent to notably improve the sampling efficiency during the learning process. With this pre-optimization, we further leverage the RL’s superior optimization ability to achieve robust device sizing by incorporating sufficient features of PVT variations into the representation learning loop. Experimental results on exemplary circuits show 3.25× ∼ 16× improvement of sampling efficiency and 6.8× ∼ 24× improvement of figure-of-merit in terms of design efficiency and design accuracy of our method, as compared to prior methods.
Language
English (en)
Chair
Xuan Zhang
Committee Members
Roger Chamberlain, Wang Chuan