Abstract
This thesis presents a manual register-transfer level (RTL) reimplementation of a high-level synthesis (HLS) data-processing pipeline for a telescope front-end system. The design processes detector data through five parallel paths, with each path performing pedestal subtraction, signal integration, and zero suppression. The processed data are then serialized and used for island detection and centroid calculation.
The RTL implementation was developed in SystemVerilog and evaluated using Xilinx Vivado. The original HLS design was examined using Vitis HLS as a reference. Individual RTL modules and the integrated system were verified using simulation testbenches covering representative inputs and important corner cases. The results show that the RTL design produces the expected signal-processing outputs and supports deterministic, cycle-level data flow. Major streaming modules can accept one 16-channel input vector per clock cycle after pipeline initialization.
Resource usage, latency, and architectural characteristics were also compared with the HLS implementation. Although the comparison is affected by differences in module boundaries and measurement scope, the RTL design provides greater visibility into pipeline behavior, interfaces, intermediate states, and resource allocation. The study demonstrates that manual RTL reimplementation can provide predictable timing and detailed architectural control, while also requiring additional design effort, verification, and system-level integration.
Committee Chair
Roger Chamberlain
Committee Members
Chris Gill Michael Hall
Degree
Master of Science (MS)
Author's Department
Computer Science & Engineering
Document Type
Thesis
Date of Award
Summer 8-13-2026
Language
English (en)
Recommended Citation
Qiao, Chuhan, "RTL Reimplementation and Performance Evaluation of an FPGA-Based Telescope Data Processing Pipeline" (2026). McKelvey School of Engineering Graduate Student Theses & Dissertations. 1399.
https://openscholarship.wustl.edu/eng_etds/1399