Data from Virtualized Hardware Logic Computations

ResourceType

Dataset

DOI

https://doi.org/10.7936/46pb-xw44

Embargo Period

4-1-2021

funderName

National Science Foundation

awardNumber

NSF grant CNS-0931693 and Exegy, Inc.

Abstract

Data files supporting paper. Paper abstract: Visualization of logic computations (i.e., by sharing a fixed function across distinct data streams) provides a means to effectively utilize hardware resources by context switching the logic to support multiple data streams of computation and to improve the total throughput of all streams. Context switching allows the pipeline stages of the logic to be fully utilized when feedback is present and to support additional contexts using secondary memory. In this paper, we analyze the performance of a virtualized hardware design and develop M/G/1 queueing model equations to predict circuit performance. The server is modeled using a general distribution that takes vacations during the computation of an individual data stream. Using the model, we predict circuit performance and tune a schedule for optimal performance.

Rights

http://creativecommons.org/publicdomain/zero/1.0/

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons 1.0 Public Domain Dedication.

Related Content

This document describes the data set associated with the journal paper:

Michael J. Hall, Neil E. Olson, and Roger D. Chamberlain, "Utilizing Virtualized Hardware Logic Computations to Benefit Multi-User Performance," Electronics, 10(6):665, 2021. DOI: 10.3390/electronics10060665

The manuscript extends the conference paper:

Michael J. Hall and Roger D. Chamberlain, "Using M/G/1 Queueing Models with Vacations to Analyze Virtualized Logic Computations," in Proc. of 33rd IEEE International Conference on Computer Design (ICCD), October 2015, pp. 86-93. DOI: 10.1109/ICCD.2015.7357087

Size

33mb

Link to Data

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Publication Date

2021