Performance Analysis and Design of a Logic Simulation Machine

Authors

Ken Wong, Washington University in St. Louis
Mark A. Franklin, Washington University in St. LouisFollow

Document Type

Technical Report

Publication Date

1986-12-01

Filename

WUCS-86-19.pdf

Technical Report Number

WUCS-86-19

Abstract

The high costs associated with logic simulation of large VLSI based circuits has led to the need for new computer architecture tailored to the simulation task. Such architectures have the potential for significant speed-ups over software-based logic simulators executing on standard sequential computers. This paper presents a model of one class of multiprocessor simulation architectures and compares the performance of some of these machines using data obtained from simulation of VLSI circuits. In addition, we discuss the implications of our results on machine design and examine the sensitivity of the model to variations in circuit characteristics.

Comments

Permanent URL: http://dx.doi.org/10.7936/K7RB72ZJ

Recommended Citation

Wong, Ken and Franklin, Mark A., "Performance Analysis and Design of a Logic Simulation Machine" Report Number: WUCS-86-19 (1986). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/835