Classical Fault Analysis of MOS VLSI Circuits

Authors

Brian L. Shing, Washington University in St. Louis
Mark A. Franklin, Washington University in St. LouisFollow

Document Type

Technical Report

Publication Date

1987-12-01

Filename

WUCS-87-32.pdf

Technical Report Number

WUCS-87-32

Abstract

Due to the large cost involved in generating effective input vectors to test MOS circuits, finding ways to reduce this test vector generation cost is of considerable interest. In this paper, empirical results show the fault coverage obtained form MOS transistor-level fault simulation using randomly generated test inputs can be approximated by the fault coverage obtained using the test vectors generated from classical stuck-at-zero and stuck-at-one fault simulation on logic-gate-level circuits. Applying this results, an approach is presented to reduce the cost of test vector generation for MOS circuits.

Comments

Permanent URL: http://dx.doi.org/10.7936/K7SX6BKQ

Recommended Citation

Shing, Brian L. and Franklin, Mark A., "Classical Fault Analysis of MOS VLSI Circuits" Report Number: WUCS-87-32 (1987). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/818