Document Type
Technical Report
Publication Date
1988-10-01
Technical Report Number
WUCS-88-32
Abstract
This paper describes the design of the Packet Buffer Chip. Packet Buffers are FIFO queues used for buffering packets and synchronizing a Switch Fabric (SF) and its associated Fiber Optic Links (FOLS) in the Broadcast Packet Switching Network. This chip will be fabricated in 2.0 UM CMOS technology.
Recommended Citation
Barrett, Neil, "Design of a VLSI Packet Buffer" Report Number: WUCS-88-32 (1988). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/789
COinS
Comments
Permanent URL: http://dx.doi.org/10.7936/K71R6NWX