Hierarchical Discrete-Event Simulation on Hypercube Architecture

Authors

Roger D. Chamberlain, Washington University in St. LouisFollow
Mark A. Franklin, Washington University in St. LouisFollow

Document Type

Technical Report

Publication Date

1988-03-01

Filename

WUCS-88-08.pdf

Technical Report Number

WUCS-88-08

Abstract

This paper presents model of hierarchical discrete-event simulation algorithm running on a hypercube architecture. We assume a static allocation of system components to processors in the hypercube. We also assume a global clock algorithm, with an event-based time increment. Following development of the performance model, we describe an application of the model in the area of digital systems simulation. Hierarchical levels included are gate level (NAND, NOR, and NOT gates) and MSI level (multiplexors, shift registers, etc.). Example values (gathered from simulations running on standard von Neumann architectures) are provided at the model inputs to show the effect of different model parameters and partitioning strategies on the simulation performance.

Comments

Permanent URL: http://dx.doi.org/10.7936/K7J67F9B

Recommended Citation

Chamberlain, Roger D. and Franklin, Mark A., "Hierarchical Discrete-Event Simulation on Hypercube Architecture" Report Number: WUCS-88-08 (1988). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/765