Design of a Gigabit ATM Switch

Authors

Tom Chaney, Washington University in St Louis
Andrew Fingerhut, Washington University in St. Louis
Margaret Flucke, Washington University in St. Louis
Jonathan S. Turner, Washington University in St. LouisFollow

Document Type

Technical Report

Department

Computer Science and Engineering

Publication Date

1996-01-01

Filename

WUCS-96-07.PDF

Technical Report Number

WUCS-96-07

Abstract

This report describes the design and implementation of a gigabit ATM switching system supporting link rates from 150 Mb/s to 2.4 Gb/s, with a uniquely efficient multicast switch architecture that enables the construction of systems with essentially constant per port costs for configurations ranging from 8 to 4096 ports and system capacities approaching 1- Tb.s. The system design supports many-to-one and many-to-many forms of multicast, in addition to the usual one-to-many. It also provides multicast virtual paths, constant time configuration of multicast connections and an efficient packet-level discard method, that can achieve 100% link efficiencies, without large buffers.

Comments

Permanent URL: http://dx.doi.org/10.7936/K79S1P86

Recommended Citation

Chaney, Tom; Fingerhut, Andrew; Flucke, Margaret; and Turner, Jonathan S., "Design of a Gigabit ATM Switch" Report Number: WUCS-96-07 (1996). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/399