Technical Report Number
This paper presents the ARAS simulator with which asynchronous instruction pipelines can be modelled, simulated and displayed. ARAS allows one to construct instruction pipelines by preparing various configuration files. Using these files and a number of benchmark programs, performance of the instruction pipelines can be obtained. The performance of asynchronous instruction pipelines can also be compared to synchronous case. Thus, one can decide the optimal design for instruction pipelines in asynchornous or synchronous cases and explore the deisng space of asynchronous instruction pipeline architectures.
Chien, Chia-Hsing and Franklin, Mark A., "Simulation of Asynchronous Instruction Pipelines" Report Number: WUCS-96-05 (1996). All Computer Science and Engineering Research.