Title

ARAS: Asynchronous RISC Architecture Simulator

Authors

Chia-Hsing Chien, Washington University in St Louis
Mark A. Franklin, Washington University in St. LouisFollow
Tienyo Pan, Washington University in St. Louis
Prithvi Prabhu, Washington University in St. Louis

Document Type

Technical Report

Department

Computer Science and Engineering

Publication Date

1995-01-01

Filename

WUCS-95-03.PDF

DOI:

10.7936/K7J964M9

Technical Report Number

WUCS-95-03

Abstract

In this paper, an asynchronous pipeline instruction simulator, ARAS is presented. With this simulator, one can design selected instruction pipelines and check their performance. Performance measurements of the pipeline configuration are obtained by simulating the execution of benchmark programs on the machine architectures developed. Depending on the simulation results obtained by using ARAS, the pipeline configuration can be altered to improve its performance. Thus, one can explore the design space of aynchronous pipeline architectures.

Comments

Permanent URL: http://dx.doi.org/10.7936/K7J964M9

Recommended Citation

Chien, Chia-Hsing; Franklin, Mark A.; Pan, Tienyo; and Prabhu, Prithvi, "ARAS: Asynchronous RISC Architecture Simulator" Report Number: WUCS-95-03 (1995). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/363