Document Type

Technical Report

Department

Computer Science and Engineering

Publication Date

2000-01-01

Filename

WUCS-00-24.PDF

Technical Report Number

WUCS-00-24

Abstract

Demands for flexible processing has moved general-purpose processing into the data path of networks. With the development of System-On-a-Chip technology, it is possible to put several processors with memory and I/O components on a single ASIC. We present a model of such a system with a simple performance metric and show how the number of processors and cache sizes can be optimized for a given workload. Based on a telecommunications benchmark we show the results of such an optimization and discuss how specialied hardware and appropriate scheduling can further improve system performance.

Comments

Permanent URL: http://dx.doi.org/10.7936/K76W98B8

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