Title

Implementation of a Pipelined Control Cell Processor

Authors

Michael Attig, Washington University in St. Louis
John W. Lockwood, Washington University in St. Louis

Document Type

Technical Report

Publication Date

2002-08-14

Filename

wucse-2002-24.pdf

DOI:

10.7936/K7FF3QQ0

Technical Report Number

WUCSE-2002-24

Abstract

A fast control cell processor (CCP) has been designed and implemented in order to process control cells as they enter the module. This fast CCP is capable of receiving back-to-back control cells, processing them, and sending them out in back-to-back fashion. The fast CCP comes equipped with a SRAM interface and a statistics interface. Currently, the fast CCP uses the Statistics Counter Plus to count the number of control cells on each VCI, the number of SRAM reads on each VCI, the number of SRAM writes on each VCI, and the total number of control cells that pass through the module.

Comments

Permanent URL: http://dx.doi.org/10.7936/K7FF3QQ0

Recommended Citation

Attig, Michael and Lockwood, John W., "Implementation of a Pipelined Control Cell Processor" Report Number: WUCSE-2002-24 (2002). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/1142