Title

Simulation of Asynchronous Instruction Pipelines

Authors

Chia-Hsing Chien, Washington University in St Louis
Mark A. Franklin, Washington University in St. LouisFollow

Document Type

Technical Report

Department

Computer Science and Engineering

Publication Date

1996-01-01

Filename

WUCS-96-05.PDF

DOI:

10.7936/K7DJ5CV4

Technical Report Number

WUCS-96-05

Abstract

This paper presents the ARAS simulator with which asynchronous instruction pipelines can be modelled, simulated and displayed. ARAS allows one to construct instruction pipelines by preparing various configuration files. Using these files and a number of benchmark programs, performance of the instruction pipelines can be obtained. The performance of asynchronous instruction pipelines can also be compared to synchronous case. Thus, one can decide the optimal design for instruction pipelines in asynchornous or synchronous cases and explore the deisng space of asynchronous instruction pipeline architectures.

Comments

Permanent URL: http://dx.doi.org/10.7936/K7DJ5CV4

Recommended Citation

Chien, Chia-Hsing and Franklin, Mark A., "Simulation of Asynchronous Instruction Pipelines" Report Number: WUCS-96-05 (1996). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/397