Design of an Interlock Module for Use in a Globally Asynchronous, Locally Synchronous Design Methodology
Technical Report Number
As the number of transistors on a single integrated circuit approach a billion, the problems of clock distribution, power consumption, multiple clock domains, meeting timing requirements, and reuse of subsystem designs grow ever more difficult. Coordinating a billion transistors with the present design methodologies will require hundreds of years of engineering time. A new design methodology is needed. The GALS (Globally Asynchronous Locally Synchronous) approach, that blends clockless and clocked subsystems is a strong contender.
Swamy, U. G.; Cox, J. R.; Engel, G. L.; and Zar, D. M., "Design of an Interlock Module for Use in a Globally Asynchronous, Locally Synchronous Design Methodology" Report Number: WUCSE-2005-52 (2005). All Computer Science and Engineering Research.
Permanent URL: http://dx.doi.org/10.7936/K7JQ0ZCZ