Technical Report Number
This project presents a novel automated framework for microprocessor instruction set exploration that allows users to extend a basic MIPS ISA with new multimedia instructions (including custom vector instructions, a la AltiVec and MMX/SSE). The infrastructure provides users with an extension language that automatically incorporates extensions into a synthesizable processor pipeline model and an executable instruction set simulator. We implement popular AltiVec and MMX extensions using this framework and present experimental results that show significant performance gains of customized microprocessor.
Kotysh, Eduard V. and Crowley, Patrick, "Processor Generator v1.3 (PG13)" Report Number: WUCSE-2005-25 (2005). All Computer Science and Engineering Research.