Document Type

Technical Report

Publication Date

1984-08-01

Filename

WUCS-84-3.pdf

DOI:

10.7936/K7ZW1J8G

Technical Report Number

WUCS-84-3

Abstract

A number of recent articles have focused on the design of high speed discrete-event simulation (DES) machines for digital logic simulation. These investigations are in response to the enormous costs associated with the simulation of complex (VLSI) digital circuits for logic verification and fault analysis. One approach to reducing simulation costs is to design special purpose digital computers that are tailored to the logic simulation test. This paper is concerned with the architecture of such logic machines. The paper has three principal parts. First, a taxonomy of logic machine architectures is presented. The taxonomy focuses on the central components of the logic simulation algorithms and on architectural alternatives for increasing the speed of the simulation process. It thus represents a basis for discussing and differentiating between proposed architectures and also results in the identification of several new architectures. Although developed for digital logic simulators., the taxonomy can be used for general DES machines. Second, a performance measure is presented which permits evaluation of DES machines. Finally several DES machine designs are described and categorized using the taxonomy.

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Permanent URL: http://dx.doi.org/10.7936/K7ZW1J8G

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