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Technical Report

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Technical Report Number



This paper considers various physical constraints which influence the design of interconnection networks used in multiprocessor systems. Design expressions are presented for implementing an N log N packet passing interconnection network composed for circuit switched crossbar chip modules. Expressions reflecting chip level and board level pin and area constraints are derived and used to determine the network delay expected at a given clock frequency. Logic and memory delay, signal path delay, clock skew and clock tree delay parameters are defined and used to determine the maximum frequency which can be obtained with a given design. An example 2048x2048 network design is considered. This example indicates that using aggressive packaging and MOS technology, a rate of about 32 MHz is achievable. However, this frequency, with this network design, would result in one way delay (ignoring blocking and hot spot delays) of about 1 usecond. A read operation from memory requiring a round trip would thus require more then 2 useconds. This represents more than an order of magnitude slowdown when compared with accessing strictly local memory and appears to be a major problem in the design of network centered multiprocessor architectures.


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