Document Type

Technical Report


Computer Science and Engineering

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Technical Report Number



We are building a very high performance 1.2 Gb/s ATM network interface chip called the APIC (ATM Port Interconnect Controller). In addition to borrowing userful ideas from a number of research and commercial prototypes, the APIC design embraces several innovative features, and integrates all of these pieces into a coherent whole. This paper describes some of the novel ideas that have been incorporated in the APIC design with a view to improving the bandwidth and latency seen by end-applications. Among the techniques described, Protected DMA and Protected I/O were designed to allow applications to queue data for transmission or reception directly from user-space, effectively bypassing the kernel. This argues for moving the entire protocol stack including the interface device driver into user-space, thereby yielding better latency and throughput performance than kernel-resident implementations. Pool DMA when used with Packet Splitting, is a technique that can be used to build true zero-copy kernel-resident protocol stack implementations, using a page-remapping technique. Orchestrated Interrupts and Interrupt Demultiplexing are mechanisms that are used to reduce the frequency of interrupts issued by the APIC; the interrupt service time itself is significantly reduced through the use of a hardware Notification Queue which is used to report the occurence of events in the APIC to software. Although our ideas have been developed in the context of an ATM network interface, we believe that many of these ideas can be effectively employed in other contexts too (including different types of network interfaces). In particular, we believe that protected DMA and protexted I/O could be used by other devices in the system, thereby facilitating the construction of microkernels that can potentially deliver better performance than their monolithic counterparts.


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