Title

Parallel FPGA Programming over Backplane Chassis

Authors

John Lockwood, Washington University in St Louis
Tom McLaughlin, Washington University in St. Louis
Tom Chaney, Washington University in St. Louis
Yuhua Chen, Washington University in St Louis
Fred Rosenberger, Washington University in St Louis
Alex Chandra, Washington University in St Louis
Jon Turner, Washington University in St LouisFollow

Document Type

Technical Report

Department

Computer Science and Engineering

Publication Date

2000-01-01

Filename

WUCS-TM-00-11.PDF

DOI:

10.7936/K7Q23XG1

Technical Report Number

WUCS-TM-00-11

Abstract

For systems with a large number of FPGAs, where a design is instantiated across multiple FPGAs in a chassis, an efficient mechanism of programming the FPGA devices is needed. The mechanism described herein allows multiple FPGAs to be programmed across a backplane. Only a single configuration PROM is required to store the configuration for the multiple instances of the design. When the system boots, all FPGAs are programmed in parallel. This design is applicable to any system which contains a multiple board system which has instances of identical FPGA implementations distributed across the boards. Signal integrity of signals is considered.

Comments

Permanent URL: http://dx.doi.org/10.7936/K7Q23XG1

Recommended Citation

Lockwood, John; McLaughlin, Tom; Chaney, Tom; Chen, Yuhua; Rosenberger, Fred; Chandra, Alex; and Turner, Jon, "Parallel FPGA Programming over Backplane Chassis" Report Number: WUCS-TM-00-11 (2000). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/294