Date of Award

Spring 5-17-2017

Author's School

School of Engineering & Applied Science

Author's Department

Electrical & Systems Engineering

Degree Name

Master of Science (MS)

Degree Type

Thesis

Abstract

Power consumption plays an important role in computer system design today. On-chip memory structures such as multi-level cache make up a significant proportion of total power consumption of CPU or Application-Specific Integrated Circuit (AISC) chip, especially for memory-intensive application, such as floating-point computation and machine learning algorithm. Therefore, there is a clear motivation to reduce power consumption of these memory structures that are mostly consisting of Static Random-Access Memory (SRAM) blocks. In this defense, I will present the framework of a novel dual-supply-voltage scheme that uses separate voltage levels for memory read and write operations. By quantitatively analyzing the cache trace for SPEC2000, Parsec, and Cortexsuite benchmarks and comparing the Read/Write sequence characterization of different computing application types, I discover that memory-intensive applications have high potential to generate long consecutive Read/Write sequences, which can be leveraged by our proposed dual-supply framework. I then perform a limit study based on ideal Read/Write re-ordering to obtain the maximum possible power saving estimate. Finally, as a case study, I apply this framework to a custom machine learning ASIC accelerator design to showcase its viability.

Language

English (en)

Chair

Xuan 'Silvia' Zhang

Committee Members

Roger Chamberlain Shantanu Chakrabartty

Comments

Permanent URL: https://doi.org/10.7936/K7S180XV