Date of Award

Spring 5-17-2017

Author's School

School of Engineering & Applied Science

Author's Department

Electrical & Systems Engineering

Degree Name

Master of Science (MS)

Degree Type

Thesis

Abstract

Power consumption becomes more and more critical in computer systems nowadays. Most of the previous work has been focusing on general-purpose computational core, but optimization techniques for conventional CPU core has reached a limit. Our experimental results show that read operations in SRAM can be performed at a lower supply with much reduced power consumption compared to write operations. Based on this observation and the fact that cache, consisting mostly of SRAM, often occupies significant on-chip area of the CPU and consumes a huge portion of the CPU power, we propose a new method to reduce the power consumption of cache. By dynamically switching the cache voltage supply between a lower voltage for read and a higher voltage for write, our method can effectively reduce cache power without affecting the performance of the multi-level cache hierarchy in a computer system. We can realize further power savings by lowering the supply below read voltage for hold-only operations when the cache is idle. Both the power switching controller implementation and the power consumption statistics from various SPEC benchmarks will be presented to demonstrate the efficiency of our proposed methods.

Language

English (en)

Chair

Xuan 'Silvia' Zhang

Committee Members

Xuan 'Silvia' Zhang Roger Chamberlain Shantanu Chakrabartty

Comments

Permanent URL: https://doi.org/10.7936/K7WS8RPB

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Engineering Commons

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