Title

Processor Generator v1.3 (PG13)

Authors

Eduard V. Kotysh, Washington University in St. Louis
Patrick Crowley, Washington University in St. LouisFollow

Document Type

Technical Report

Publication Date

2005-05-30

Filename

WUCSE-2005-25.pdf

DOI:

10.7936/K7V69GWX

Technical Report Number

WUCSE-2005-25

Abstract

This project presents a novel automated framework for microprocessor instruction set exploration that allows users to extend a basic MIPS ISA with new multimedia instructions (including custom vector instructions, a la AltiVec and MMX/SSE). The infrastructure provides users with an extension language that automatically incorporates extensions into a synthesizable processor pipeline model and an executable instruction set simulator. We implement popular AltiVec and MMX extensions using this framework and present experimental results that show significant performance gains of customized microprocessor.

Comments

Permanent URL: http://dx.doi.org/10.7936/K7V69GWX

Recommended Citation

Kotysh, Eduard V. and Crowley, Patrick, "Processor Generator v1.3 (PG13)" Report Number: WUCSE-2005-25 (2005). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/943