Statistics on Logic Simulation

Authors

K. F. Wong, Washington University in St. Louis
Mark A. Franklin, Washington University in St. LouisFollow
Roger D. Chamberlain, Washington University in St. LouisFollow
B. L. Shing, Washington University in St. Louis

Document Type

Technical Report

Publication Date

1985-11-01

Filename

WUCS-85-09.pdf

DOI:

10.7936/K7FF3QPJ

Technical Report Number

WUCS-85-09

Abstract

The high costs associated with logic simulation of large VLSI based systems have led to the need for new computer architectures tailored to the simulation task. Such architecture have the potential for significant speedups over standard software based logic simulators. Several commercial simulation engines have been produced to satisfy need in this area. To properly explore the space of alternative simulation architectures, data is required on the simulation process itself. This paper presents a framework for such data gathering activity by first examining possible sources of speedup in the logic simulation task, examining the sort of data needed in the design of simulation engines, and then presenting such data. The data contained in the paper includes information on the subtask times found in standard discrete event simulation algorithms, event intensities, queue length distributions and simultaneous event distributions.

Comments

Permanent URL: http://dx.doi.org/10.7936/K7FF3QPJ

Recommended Citation

Wong, K. F.; Franklin, Mark A.; Chamberlain, Roger D.; and Shing, B. L., "Statistics on Logic Simulation" Report Number: WUCS-85-09 (1985). All Computer Science and Engineering Research.
https://openscholarship.wustl.edu/cse_research/853